library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity du is
	port (
		empty0 : in std_logic;
		empty1 : in std_logic;
		empty2 : in std_logic;
		empty3 : in std_logic;
		requestrd: in std_logic;
		sel    : out std_logic_vector(1 downto 0);
		rdreq0 : out std_logic;
		rdreq1 : out std_logic;
		rdreq2 : out std_logic;
		rdreq3 : out std_logic;
		emptyall: out std_logic;
		emptyone: out std_logic);
end du;

architecture RTL of du is
	signal en   : std_logic;
	signal em   : std_logic;
	signal count: std_logic_vector(1 downto 0);
begin
	em <= not (empty0 and empty1 and empty2 and empty3);
	process(requestrd,empty0,empty1,empty2,empty3)
	begin
		if (requestrd'event and requestrd='1') then
			en <= '1';
			count <= count + 1;
		end if;
		if (em = '0') then
			rdreq0 <= '0';
			rdreq1 <= '0';
			rdreq2 <= '0';
			rdreq3 <= '0';
			en <='0';
		end if;
		if (en = '1') then
			if (count = "00") then			
				if (empty0 = '0') then	
					sel <= "00";
					rdreq0 <= '1';
					rdreq1 <= '0';
					rdreq2 <= '0';
					rdreq3 <= '0';
					emptyone <= '0';
				else 
					emptyone <= '1';
					rdreq0 <= '0';
					rdreq1 <= '0';
					rdreq2 <= '0';
					rdreq3 <= '0';
				end if;
			elsif (count = "01") then
				if (empty1='0') then
					sel <= "01";
					rdreq0 <= '0';
					rdreq1 <= '1';
					rdreq2 <= '0';
					rdreq3 <= '0';
					emptyone <= '0';
				else 
					emptyone <= '1';
					rdreq0 <= '0';
					rdreq1 <= '0';
					rdreq2 <= '0';
					rdreq3 <= '0';
				end if;
			elsif (count = "10") then
				if (empty2='0') then
					sel <= "10";
					rdreq0 <= '0';
					rdreq1 <= '0';
					rdreq2 <= '1';
					rdreq3 <= '0';
					emptyone <= '0';
				else 
					emptyone <= '1';
					rdreq0 <= '0';
					rdreq1 <= '0';
					rdreq2 <= '0';
					rdreq3 <= '0';
				end if;
			elsif (count = "10") then
				else if (empty3='0') then
					sel <= "11";
					rdreq0 <= '0';
					rdreq1 <= '0';
					rdreq2 <= '0';
					rdreq3 <= '1';
					emptyone <= '0';
				else 
					emptyone <= '1';
					rdreq0 <= '0';
					rdreq1 <= '0';
					rdreq2 <= '0';
					rdreq3 <= '0';
				end if;
			end if;	
		end if;
		emptyall <= em;
 	end process;
end RTL;